TWO i/p (8bitwide) COMPARATOR:- 

module comp8 (gt8,eq8,lt8,A8,B8);
input[7:0]A8,B8;
output gt8,eq8,lt8;
wire [2:0]Y22;
wire a8,b8,c8,d8,e8,f8;
comp4 co11 (a8,b8,c8,{A8[7],A8[6],A8[5],A8[4]},{B8[7],B8[6],B8[5],B8[4]});
comp4 co22 (d8,e8,f8,{A8[3],A8[2],A8[1],A8[0]},{B8[3],B8[2],B8[1],B8[0]});
mux2x1_3b mm1 ({gt8,eq8,lt8},a8,Y22,3'b100);
mux2x1_3b mm2 (Y22,c8,{d8,e8,f8},3'b001);
endmodule

TEST BENCH:- 

module comp8_tb();
reg [7:0]A8,B8;
wire gt8,eq8,lt8;
comp8 dut (gt8,eq8,lt8,A8,B8);
initial
begin
repeat(20)
begin
{A8,B8}=$random;
#2
$display("A=",{A8}," B=",{B8},":"," greater:",gt8," equal:",eq8," lesser:",lt8);
end
end
endmodule

 

2I/P- 5BIT WIDE SUBTRACTOR 

module sub_5b (bor,diff,A,B);
input [4:0] A,B;
output [4:0]diff;
output bor;
wire[4:0]b1,b2;

not n1 (b1[0],B[0]);//(1scomp)
not n2 (b1[1],B[1]);//(1scomp)
not n3 (b1[2],B[2]);//(1scomp)
not n4 (b1[3],B[3]);//(1scomp)
not n5 (b1[4],B[4]);//(1scomp)

add2_5b ad1 (unused,b2,5'b00001,b1);  //(1scomp+1)

add2_5b ad2 (bor,diff,A,b2); //((2scomp of B) + A)
endmodule 

logic:- 1st do 1s comp and perform 2s comp for B and add with A. 

sub modules :- 5 i/p adder module

TEST BENCH:-

module sub2_5b_tb();
reg [4:0]A,B;
wire [4:0]diff;
wire bor;
sub_5b dut (bor,diff,A,B);
initial
begin
repeat(20)
begin
A=$random;
B=$urandom_range(A,0);
#1;
$display({A}," ",{B},":",{diff});
end
end
endmodule

  

 

TWO i/p (4bitwide) COMPARATOR:- 

module comp4 (gt4,eq4,lt4,A4,B4);
input[3:0]A4,B4;
output gt4,eq4,lt4;
wire [2:0]Y1;
wire a4,b4,c4,d4,e4,f4;
comp2 co1 (a4,b4,c4,{A4[3],A4[2]},{B4[3],B4[2]});
comp2 co2 (d4,e4,f4,{A4[1],A4[0]},{B4[1],B4[0]});
mux2x1_3b m1 ({gt4,eq4,lt4},a4,Y1,3'b100);
mux2x1_3b m2 (Y1,c4,{d4,e4,f4},3'b001);
endmodule

TEST BENCH:- 

module comp4_tb();
reg [3:0]A4,B4;
wire gt4,eq4,lt4;
comp4 dut (gt4,eq4,lt4,A4,B4);
initial
begin
repeat(20)
begin
{A4,B4}=$random;
#2
$display("A=",{A4}," B=",{B4},":"," greater:",gt4," equal:",eq4," lesser:",lt4);
end
end
endmodule

 

 

TWO i/p (2bitwide) COMPARATOR:- 

module comp2(gt2,eq2,lt2,A2,B2);
input[1:0]A2,B2;
output gt2,eq2,lt2;
wire [2:0]Y1;
wire a,b,c,d,e,f;
comp1  c1 (a,b,c,A2[1],B2[1]);
comp1  c2  (d,e,f,A2[0],B2[0]);
mux2x1_3b m1 ({gt2,eq2,lt2},a,Y1,3'b100);
mux2x1_3b m2 (Y1,c,{d,e,f},3'b001);
endmodule

TEST BENCH:- 

module comp2_tb();
reg [1:0]A2,B2;
wire gt2,eq2,lt2;
comp2 dut (gt2,eq2,lt2,A2,B2);
initial
begin
repeat(20)
begin
{A2,B2}=$random;
#2
$display("A=",{A2}," B=",{B2},":","greater:",gt2,"equal:",eq2,"lesser:",lt2);
end
end
endmodule

MUX2x1(3bit wide):-

  MUX 2:1 :-

//s-select line ; Y-output ; I0,I1 -input lines

module mux2x1 (y,s,i0,i1); 
input s,i1,i0;
output y;
assign y=((~s)&(i0))+((s)&(i1));
endmodule

 MUX2x1(3bit wide):-

module mux2x1_3b(Y,s,I0,I1);
input[2:0]I0,I1;
input s;
output [2:0]Y;
mux2x1 m1 (Y[0],s,I0[0],I1[0]); 
mux2x1 m2 (Y[1],s,I0[1],I1[1]); 
mux2x1 m3 (Y[2],s,I0[2],I1[2]);
endmodule 

 MUX 4:1 Testbench:-

module mux2x1_3b_tb();
reg s;
reg [2:0] I1,I0;
wire [2:0] Y;
mux2x1_3b dut (Y,s,I0,I1);
initial
begin
repeat(20)
begin
{s,I0,I1}=$random;
#2
$display(s,I0,I1,":",Y);
end
end
endmodule

 

2I/P- A-1bit; B-5BIT WIDE ADDER 

module add2_5b (co1,s,a,b);
input [4:0]b;
input a;
output [4:0]s;
output co1;
fa ra1 (c0,s[0],a,b[0],1'b0);
fa ra2 (c1,s[1],1'b0,b[1],c0);
fa ra3 (c2,s[2],1'b0,b[2],c1);
fa ra4 (c3,s[3],1'b0,b[3],c2);
fa ra5 (co1,s[4],1'b0,b[4],c3);
endmodule

TEST BENCH:-

module add2_5b_tb();
reg [4:0]a,b;
wire [4:0]s;
wire c;
add2_5b dut (c,s,a,b);
initial
begin
repeat(20)
begin
a=$random;
b=$random;
#1;
$display({a}," ",{b},":",{c,s});
end
end
endmodule

2I/P- 5BIT WIDE ADDER 

module add2_5b (c1,s,a,b);
input [4:0]a,b;
output [4:0]s;
output c1;
fa ra1 (c0,s[0],a[0],b[0],1'b0);
fa ra2 (c1,s[1],a[1],b[1],c0);
fa ra3 (c2,s[2],a[2],b[2],c1);
fa ra4 (c3,s[3],a[3],b[3],c2);
fa ra5 (c1,s[4],a[4],b[4],c3);
endmodule

TEST BENCH:-

module add2_5b_tb();
reg [4:0]a,b;
wire [4:0]s;
wire c;
add2_5b dut (c,s,a,b);
initial
begin
repeat(20)
begin
a=$random;
b=$random;
#1;
$display({a}," ",{b},":",{c,s});
end
end
endmodule

 

TWO BIT COMPARATOR:- 

(one bit wide)

module comp1 (gt,eq,lt,a,b);
input a,b;
output gt,eq,lt;
not G1(abar,a);
not G2(bbar,b);
and G3(gt,a,bbar);
and G4(lt,abar,b);
xnor G5(eq,a,b);
endmodule

TEST BENCH:- 

module comp1_tb();

reg a,b;
wire gt,eq,lt;
comp1 dut (gt,eq,lt,a,b);
initial
begin
repeat(20)
begin
a=$random;
b=$random;
#1;
$display(a,b,":",gt,eq,lt);
end
end
endmodule

 8X8 MULTIPLIER:-

module mul8(Y,a,b);
input [7:0]a,b;
output [16:0]Y;

and g00 (Y[0],a[0],b[0]);
and g01 (p01 ,a[1],b[0]);
and g02 (p02 ,a[2],b[0]);
and g03 (p03 ,a[3],b[0]);
and g04 (p04 ,a[4],b[0]);
and g05 (p05 ,a[5],b[0]);
and g06 (p06 ,a[6],b[0]);
and g07 (p07 ,a[7],b[0]);

and g10 (p10,a[0],b[1]);
and g11 (p11 ,a[1],b[1]);
and g12 (p12 ,a[2],b[1]);
and g13 (p13 ,a[3],b[1]);
and g14 (p14 ,a[4],b[1]);
and g15 (p15 ,a[5],b[1]);
and g16 (p16 ,a[6],b[1]);
and g17 (p17 ,a[7],b[1]);

and g20 (p20,a[0],b[2]);
and g21 (p21 ,a[1],b[2]);
and g22 (p22 ,a[2],b[2]);
and g23 (p23 ,a[3],b[2]);
and g24 (p24 ,a[4],b[2]);
and g25 (p25 ,a[5],b[2]);
and g26 (p26 ,a[6],b[2]);
and g27 (p27 ,a[7],b[2]);

and g30 (p30,a[0],b[3]);
and g31 (p31 ,a[1],b[3]);
and g32 (p32 ,a[2],b[3]);
and g33 (p33 ,a[3],b[3]);
and g34 (p34 ,a[4],b[3]);
and g35 (p35 ,a[5],b[3]);
and g36 (p36 ,a[6],b[3]);
and g37 (p37 ,a[7],b[3]);
and g40 (p40,a[0],b[4]);
and g41 (p41 ,a[1],b[4]);
and g42 (p42 ,a[2],b[4]);
and g43 (p43 ,a[3],b[4]);
and g44 (p44 ,a[4],b[4]);
and g45 (p45 ,a[5],b[4]);
and g46 (p46 ,a[6],b[4]);
and g47 (p47 ,a[7],b[4]);
and g50 (p50,a[0],b[5]);
and g51 (p51 ,a[1],b[5]);
and g52 (p52 ,a[2],b[5]);
and g53 (p53 ,a[3],b[5]);
and g54 (p54 ,a[4],b[5]);
and g55 (p55 ,a[5],b[5]);
and g56 (p56 ,a[6],b[5]);
and g57 (p57 ,a[7],b[5]);
and g60 (p60,a[0],b[6]);
and g61 (p61 ,a[1],b[6]);
and g62 (p62 ,a[2],b[6]);
and g63 (p63 ,a[3],b[6]);
and g64 (p64 ,a[4],b[6]);
and g65 (p65 ,a[5],b[6]);
and g66 (p66 ,a[6],b[6]);
and g67 (p67 ,a[7],b[6]);
and g70 (p70,a[0],b[7]);
and g71 (p71 ,a[1],b[7]);
and g72 (p72 ,a[2],b[7]);
and g73 (p73 ,a[3],b[7]);
and g74 (p74 ,a[4],b[7]);
and g75 (p75 ,a[5],b[7]);
and g76 (p76 ,a[6],b[7]);
and g77 (p77 ,a[7],b[7]);
ha a1 (c1,Y[1],p10,p01);
xfa a2 (c21,c20,Y[2],p20,c1,p11,p02); 
xlfa a3 (c31,c30,Y[3],c20,p30,p21,p12,p03);
add7  a4 (c41,c40,Y[4],c21,c30,p40,p31,p22,p13,p04);
add8 a5 (c52,c51,c50,Y[5],c31,c40,p50,p41,p32,p23,p14,p05);
add9 a6 (c62,c61,c60,Y[6],c41,c50,p60,p51,p42,p33,p24,p15,p06);
add10 a7 (c72,c71,c70,Y[7],c51,c60,p70,p61,p52,p43,p34,p25,p16,p07);
add10 a8 (c82,c81,c80,Y[8],c52,c61,c70,p71,p62,p53,p44,p35,p26,p17);
add9 a9 (c92,c91,c90,Y[9],c71,c62,c80,p72,p63,p54,p45,p36,p27);
add8 a10 (c102,c101,c100,Y[10],c90,c81,c72,p73,p64,p55,p46,p37);
add7 a11 (c111,c110,Y[11],c100,c91,c82,p74,p65,p56,p47);
add6 a12 (c121,c120,Y[12],c110,c101,c92,p75,p66,p57);
xlfa a13 (c131,c130,Y[13],c120,c111,c102,p76,p66);
fa   a14 (c140,Y[14],c130,c121,p77);
ha   a15 (c150,Y[15],c140,c131); 
ha   a16  (c160,Y[16],c150,1'b0);
endmodule

TEST BENCH:-

module adtb ();
reg [7:0]a,b;
wire [16:0]Y;
mul8 dut (Y,a,b);
initial
repeat(20)
begin
a=$random;
b=$random;
#1;
//$display("%b %b %b ", a,b,Y);
#1;
$display(a, " x " ," ", b ," : ", Y);
end
endmodule