TWO i/p (4bitwide) COMPARATOR:- 

module comp4 (gt4,eq4,lt4,A4,B4);
input[3:0]A4,B4;
output gt4,eq4,lt4;
wire [2:0]Y1;
wire a4,b4,c4,d4,e4,f4;
comp2 co1 (a4,b4,c4,{A4[3],A4[2]},{B4[3],B4[2]});
comp2 co2 (d4,e4,f4,{A4[1],A4[0]},{B4[1],B4[0]});
mux2x1_3b m1 ({gt4,eq4,lt4},a4,Y1,3'b100);
mux2x1_3b m2 (Y1,c4,{d4,e4,f4},3'b001);
endmodule

TEST BENCH:- 

module comp4_tb();
reg [3:0]A4,B4;
wire gt4,eq4,lt4;
comp4 dut (gt4,eq4,lt4,A4,B4);
initial
begin
repeat(20)
begin
{A4,B4}=$random;
#2
$display("A=",{A4}," B=",{B4},":"," greater:",gt4," equal:",eq4," lesser:",lt4);
end
end
endmodule

 

 

TWO i/p (2bitwide) COMPARATOR:- 

module comp2(gt2,eq2,lt2,A2,B2);
input[1:0]A2,B2;
output gt2,eq2,lt2;
wire [2:0]Y1;
wire a,b,c,d,e,f;
comp1  c1 (a,b,c,A2[1],B2[1]);
comp1  c2  (d,e,f,A2[0],B2[0]);
mux2x1_3b m1 ({gt2,eq2,lt2},a,Y1,3'b100);
mux2x1_3b m2 (Y1,c,{d,e,f},3'b001);
endmodule

TEST BENCH:- 

module comp2_tb();
reg [1:0]A2,B2;
wire gt2,eq2,lt2;
comp2 dut (gt2,eq2,lt2,A2,B2);
initial
begin
repeat(20)
begin
{A2,B2}=$random;
#2
$display("A=",{A2}," B=",{B2},":","greater:",gt2,"equal:",eq2,"lesser:",lt2);
end
end
endmodule

 

TWO BIT COMPARATOR:- 

(one bit wide)

module comp1 (gt,eq,lt,a,b);
input a,b;
output gt,eq,lt;
not G1(abar,a);
not G2(bbar,b);
and G3(gt,a,bbar);
and G4(lt,abar,b);
xnor G5(eq,a,b);
endmodule

TEST BENCH:- 

module comp1_tb();

reg a,b;
wire gt,eq,lt;
comp1 dut (gt,eq,lt,a,b);
initial
begin
repeat(20)
begin
a=$random;
b=$random;
#1;
$display(a,b,":",gt,eq,lt);
end
end
endmodule