Thursday, January 26, 2023

  

 

TWO i/p (4bitwide) COMPARATOR:- 


module comp4 (gt4,eq4,lt4,A4,B4);
input[3:0]A4,B4;
output gt4,eq4,lt4;
wire [2:0]Y1;
wire a4,b4,c4,d4,e4,f4;
comp2 co1 (a4,b4,c4,{A4[3],A4[2]},{B4[3],B4[2]});
comp2 co2 (d4,e4,f4,{A4[1],A4[0]},{B4[1],B4[0]});
mux2x1_3b m1 ({gt4,eq4,lt4},a4,Y1,3'b100);
mux2x1_3b m2 (Y1,c4,{d4,e4,f4},3'b001);
endmodule


TEST BENCH:- 

module comp4_tb();
reg [3:0]A4,B4;
wire gt4,eq4,lt4;
comp4 dut (gt4,eq4,lt4,A4,B4);
initial
begin
repeat(20)
begin
{A4,B4}=$random;
#2
$display("A=",{A4}," B=",{B4},":"," greater:",gt4," equal:",eq4," lesser:",lt4);
end
end
endmodule















No comments:

Post a Comment

VERILOG CODES :-

 VERILOG CODES :- (by NUTAN.K) COMBINATIONAL :-  1.MUX:- (one bit wide)  1a) 2:1 MUX and its Testbench   1b) 4:1 MUX using 2:1 and its testb...