MUX2x1(3bit wide):-

  MUX 2:1 :-

//s-select line ; Y-output ; I0,I1 -input lines

module mux2x1 (y,s,i0,i1); 
input s,i1,i0;
output y;
assign y=((~s)&(i0))+((s)&(i1));
endmodule

 MUX2x1(3bit wide):-

module mux2x1_3b(Y,s,I0,I1);
input[2:0]I0,I1;
input s;
output [2:0]Y;
mux2x1 m1 (Y[0],s,I0[0],I1[0]); 
mux2x1 m2 (Y[1],s,I0[1],I1[1]); 
mux2x1 m3 (Y[2],s,I0[2],I1[2]);
endmodule 

 MUX 4:1 Testbench:-

module mux2x1_3b_tb();
reg s;
reg [2:0] I1,I0;
wire [2:0] Y;
mux2x1_3b dut (Y,s,I0,I1);
initial
begin
repeat(20)
begin
{s,I0,I1}=$random;
#2
$display(s,I0,I1,":",Y);
end
end
endmodule

 

2I/P- A-1bit; B-5BIT WIDE ADDER 

module add2_5b (co1,s,a,b);
input [4:0]b;
input a;
output [4:0]s;
output co1;
fa ra1 (c0,s[0],a,b[0],1'b0);
fa ra2 (c1,s[1],1'b0,b[1],c0);
fa ra3 (c2,s[2],1'b0,b[2],c1);
fa ra4 (c3,s[3],1'b0,b[3],c2);
fa ra5 (co1,s[4],1'b0,b[4],c3);
endmodule

TEST BENCH:-

module add2_5b_tb();
reg [4:0]a,b;
wire [4:0]s;
wire c;
add2_5b dut (c,s,a,b);
initial
begin
repeat(20)
begin
a=$random;
b=$random;
#1;
$display({a}," ",{b},":",{c,s});
end
end
endmodule

2I/P- 5BIT WIDE ADDER 

module add2_5b (c1,s,a,b);
input [4:0]a,b;
output [4:0]s;
output c1;
fa ra1 (c0,s[0],a[0],b[0],1'b0);
fa ra2 (c1,s[1],a[1],b[1],c0);
fa ra3 (c2,s[2],a[2],b[2],c1);
fa ra4 (c3,s[3],a[3],b[3],c2);
fa ra5 (c1,s[4],a[4],b[4],c3);
endmodule

TEST BENCH:-

module add2_5b_tb();
reg [4:0]a,b;
wire [4:0]s;
wire c;
add2_5b dut (c,s,a,b);
initial
begin
repeat(20)
begin
a=$random;
b=$random;
#1;
$display({a}," ",{b},":",{c,s});
end
end
endmodule

 11 i/p (1bit wide) ADDER:-

module add11 (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h,i,j,k);
input a,b,c,d,e,f,g,h,i,j,k;
output cout3,cout2,cout1,s;
add10 ad1 (c3,c2,c1,s1,a,b,c,d,e,f,g,h,i,j);
ha h1 (c4,s,s1,k);
ha h2 (c5,cout1,c4,c1);
ha h3 (c6,cout2,c5,c2);
ha h4 (c7,cout3,c6,c3);
endmodule

 TEST BENCH:-

module adtb ();
reg a,b,c,d,e,f,g,h,i,j,k;
wire cout3,cout2,cout1,s;
add11 dut (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h,i,j,k);
integer z;
initial
begin
for (z=0;z<=2047;z=z+1)
begin
{a,b,c,d,e,f,g,h,i,j,k}= z;
#1;
$display(a,b,c,d,e,f,g,h,i,j,k,":",cout3,cout2,cout1,s);
end
end
endmodule

 10 i/p (1bit wide) ADDER:-

module add10 (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h,i,j);
input a,b,c,d,e,f,g,h,i,j;
output cout3,cout2,cout1,s;
add9 ad1 (c3,c2,c1,s1,a,b,c,d,e,f,g,h,i);
ha h1 (c4,s,s1,j);
ha h2 (c5,cout1,c4,c1);
ha h3 (c6,cout2,c5,c2);
ha h4 (c7,cout3,c6,c3);
endmodule

 TEST BENCH:-

module adtb ();
reg a,b,c,d,e,f,g,h,i,j;
wire cout3,cout2,cout1,s;
add10 dut (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h,i,j);
integer z;
initial
begin
for (z=0;z<=1023;z=z+1)
begin
{a,b,c,d,e,f,g,h,i,j}= z;
#1;
$display(a,b,c,d,e,f,g,h,i,j,":",cout3,cout2,cout1,s);
end
end
endmodule

 9 i/p ADDER (1bit wide) :-

module add9 (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h,i);
input a,b,c,d,e,f,g,h,i;
output cout3,cout2,cout1,s;
add8 ad1 (c3,c2,c1,s1,a,b,c,d,e,f,g,h);
ha h1 (c4,s,s1,i);
ha h2 (c5,cout1,c4,c1);
ha h3 (c6,cout2,c5,c2);
ha h4 (c7,cout3,c6,c3);
endmodule

TEST BENCH :-

module adtb ();
reg a,b,c,d,e,f,g,h,i;
wire cout2,cout1,s;
add9 dut (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h,i);
integer z;
initial
begin
for (z=0;z<=511;z=z+1)
begin
{a,b,c,d,e,f,g,h,i}= z;
#1;
$display(a,b,c,d,e,f,g,h,i,":",cout3,cout2,cout1,s);
end
end
endmodule

  8 i/p (1bit wide) ADDER:-

module add8 (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h);
input a,b,c,d,e,f,g,h;
output cout3,cout2,cout1,s;
add7 ad1 (c2,c1,s1,a,b,c,d,e,f,g);
ha h1 (c3,s,s1,h);
ha h2 (c4,cout1,c3,c1);
ha h3 (cout3,cout2,c4,c2);
endmodule

Testbench :-

module adtb ();
reg a,b,c,d,e,f,g,h;
wire cout2,cout1,s;
add8 dut (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h);
integer j;
initial
begin
for (j=0;j<=255;j=j+1)
begin
{a,b,c,d,e,f,g,h}= j;
#1;
$display(a,b,c,d,e,f,g,h,":",cout3,cout2,cout1,s);
end
end
endmodule

 7 i/p (1bit wide) ADDER:-

module add7 (cout2,cout1,s,a,b,c,d,e,f,g);
input a,b,c,d,e,f,g;
output cout2,cout1,s;
add6 ad1 (c2,c1,s1,a,b,c,d,e,f);
ha h1 (c3,s,s1,g);
ha h2 (c4,cout1,c3,c1);
ha h3 (c5,cout2,c4,c2);
endmodule

 Testbench :-

module adtb ();

reg a,b,c,d,e,f,g;

wire cout2,cout1,s;

add7 dut (cout2,cout1,s,a,b,c,d,e,f,g);

integer j;

initial

begin

for (j=0;j<=127;j=j+1)

begin

{a,b,c,d,e,f,g}= j;

#1;

$display(a,b,c,d,e,f,g,":",cout2,cout1,s);

end

end

endmodule

 6 i/p - 1bit wide ADDER:-

module add6 (cout2,cout1,s,a,b,c,d,e,f);
input a,b,c,d,e,f;
output cout2,cout1,s;
xlfa xl1 (c2,c1,s1,a,b,c,d,e);
ha h1 (c3,s,s1,f);
ha h2 (c4,cout1,c3,c1);
ha h3 (c5,cout2,c4,c2);
endmodule

 Test Bench:-

module adtb ();
reg a,b,c,d,e,f;
wire cout2,cout1,s;
add6 dut (cout2,cout1,s,a,b,c,d,e,f);
integer j;
initial
begin
for (j=0;j<=63;j=j+1)
begin
{a,b,c,d,e,f}= j;
#1;
$display(a,b,c,d,e,f,":",cout2,cout1,s);
end
end
endmodule

 XL-FA :- (5i/p -1bitwide adder):-

module xlfa(cout2,cout1,s,a,b,c,d,e);
input a,b,c,d,e;
output cout2,cout1,s;
xfa xf1 (c2,c1,s1,a,b,c,d); 
ha h1 (c3,s,s1,e);
ha h2 (c4,cout1,c3,c1);
ha h3 (c5,cout2,c4,c2);
endmodule

Test bench:-

module adtb ();
reg a,b,c,d,e;
wire cout2,cout1,s;
xlfa dut (cout2,cout1,s,a,b,c,d,e);
integer j;
initial
begin
for (j=0;j<=31;j=j+1)
begin
{a,b,c,d,e}= j;
#1;
$display(a,b,c,d,e,":",cout2,cout1,s);
end
end
endmodule

 X-FULL ADDER:- (4i/p-1bitwide adder)

module xfa (cout2,cout1,s,a,b,c,d); 
input a,b,c,d;
output cout2,cout1,s;
wire c1,s1,c2;
fa f1 (c1,s1,a,b,c);
ha h1 (c2,s,s1,d);
ha h2 (cout2,cout1,c1,c2);
endmodule

 TEST BENCH:-

module adtb ();

reg a,b,c,d;
wire cout2,cout1,s;
xfa dut (cout2,cout1,s,a,b,c,d); 
integer j;
initial
begin
for (j=0;j<=15;j=j+1)
begin
{a,b,c,d}= j;
#1;
$display(a,b,c,d,":",cout2,cout1,s);
end
end
endmodule

FULL ADDER:- 

module fa(cout,s,a,b,cin);
input a,b,cin;
output cout,s;
xor x1(s,a,b,cin);
and a1(c1,a,b);
and a2(c2,b,cin);
and a3(c3,cin,a);
or o1(cout,c1,c2,c3);
endmodule

TEST BENCH:- 

module adtb ();
reg a,b,cin;
wire cout,s;

fa dut (cout,s,a,b,cin);

integer j;
initial
begin
for (j=0;j<=7;j=j+1)
begin
{a,b,cin}= j;
#1;
$display(a,b,cin,":",cout,s);
end
end
endmodule

 HALF ADDER:- 

module ha(c,s,a,b);
input a,b;
output s,c;
xor x1(s,a,b);
and a1 (c,a,b);
endmodule

Testbench:- 

module hatb ();
reg a,b;
wire c,s;
ha dut (c,s,a,b);
integer i;
initial
begin
for (i=0;i<=3;i=i+1)
begin
{a,b}= i;
#1;
$display(a,b,":",c,s);
end
end
endmodule