Sunday, January 1, 2023

 8X8 MULTIPLIER:-




module mul8(Y,a,b);
input [7:0]a,b;
output [16:0]Y;

and g00 (Y[0],a[0],b[0]);
and g01 (p01 ,a[1],b[0]);
and g02 (p02 ,a[2],b[0]);
and g03 (p03 ,a[3],b[0]);
and g04 (p04 ,a[4],b[0]);
and g05 (p05 ,a[5],b[0]);
and g06 (p06 ,a[6],b[0]);
and g07 (p07 ,a[7],b[0]);

and g10 (p10,a[0],b[1]);
and g11 (p11 ,a[1],b[1]);
and g12 (p12 ,a[2],b[1]);
and g13 (p13 ,a[3],b[1]);
and g14 (p14 ,a[4],b[1]);
and g15 (p15 ,a[5],b[1]);
and g16 (p16 ,a[6],b[1]);
and g17 (p17 ,a[7],b[1]);

and g20 (p20,a[0],b[2]);
and g21 (p21 ,a[1],b[2]);
and g22 (p22 ,a[2],b[2]);
and g23 (p23 ,a[3],b[2]);
and g24 (p24 ,a[4],b[2]);
and g25 (p25 ,a[5],b[2]);
and g26 (p26 ,a[6],b[2]);
and g27 (p27 ,a[7],b[2]);

and g30 (p30,a[0],b[3]);
and g31 (p31 ,a[1],b[3]);
and g32 (p32 ,a[2],b[3]);
and g33 (p33 ,a[3],b[3]);
and g34 (p34 ,a[4],b[3]);
and g35 (p35 ,a[5],b[3]);
and g36 (p36 ,a[6],b[3]);
and g37 (p37 ,a[7],b[3]);
and g40 (p40,a[0],b[4]);
and g41 (p41 ,a[1],b[4]);
and g42 (p42 ,a[2],b[4]);
and g43 (p43 ,a[3],b[4]);
and g44 (p44 ,a[4],b[4]);
and g45 (p45 ,a[5],b[4]);
and g46 (p46 ,a[6],b[4]);
and g47 (p47 ,a[7],b[4]);
and g50 (p50,a[0],b[5]);
and g51 (p51 ,a[1],b[5]);
and g52 (p52 ,a[2],b[5]);
and g53 (p53 ,a[3],b[5]);
and g54 (p54 ,a[4],b[5]);
and g55 (p55 ,a[5],b[5]);
and g56 (p56 ,a[6],b[5]);
and g57 (p57 ,a[7],b[5]);
and g60 (p60,a[0],b[6]);
and g61 (p61 ,a[1],b[6]);
and g62 (p62 ,a[2],b[6]);
and g63 (p63 ,a[3],b[6]);
and g64 (p64 ,a[4],b[6]);
and g65 (p65 ,a[5],b[6]);
and g66 (p66 ,a[6],b[6]);
and g67 (p67 ,a[7],b[6]);
and g70 (p70,a[0],b[7]);
and g71 (p71 ,a[1],b[7]);
and g72 (p72 ,a[2],b[7]);
and g73 (p73 ,a[3],b[7]);
and g74 (p74 ,a[4],b[7]);
and g75 (p75 ,a[5],b[7]);
and g76 (p76 ,a[6],b[7]);
and g77 (p77 ,a[7],b[7]);
ha a1 (c1,Y[1],p10,p01);
xfa a2 (c21,c20,Y[2],p20,c1,p11,p02); 
xlfa a3 (c31,c30,Y[3],c20,p30,p21,p12,p03);
add7  a4 (c41,c40,Y[4],c21,c30,p40,p31,p22,p13,p04);
add8 a5 (c52,c51,c50,Y[5],c31,c40,p50,p41,p32,p23,p14,p05);
add9 a6 (c62,c61,c60,Y[6],c41,c50,p60,p51,p42,p33,p24,p15,p06);
add10 a7 (c72,c71,c70,Y[7],c51,c60,p70,p61,p52,p43,p34,p25,p16,p07);
add10 a8 (c82,c81,c80,Y[8],c52,c61,c70,p71,p62,p53,p44,p35,p26,p17);
add9 a9 (c92,c91,c90,Y[9],c71,c62,c80,p72,p63,p54,p45,p36,p27);
add8 a10 (c102,c101,c100,Y[10],c90,c81,c72,p73,p64,p55,p46,p37);
add7 a11 (c111,c110,Y[11],c100,c91,c82,p74,p65,p56,p47);
add6 a12 (c121,c120,Y[12],c110,c101,c92,p75,p66,p57);
xlfa a13 (c131,c130,Y[13],c120,c111,c102,p76,p66);
fa   a14 (c140,Y[14],c130,c121,p77);
ha   a15 (c150,Y[15],c140,c131); 
ha   a16  (c160,Y[16],c150,1'b0);
endmodule


TEST BENCH:-

module adtb ();
reg [7:0]a,b;
wire [16:0]Y;
mul8 dut (Y,a,b);
initial
repeat(20)
begin
a=$random;
b=$random;
#1;
//$display("%b %b %b ", a,b,Y);
#1;
$display(a, " x " ," ", b ," : ", Y);
end
endmodule






No comments:

Post a Comment

VERILOG CODES :-

 VERILOG CODES :- (by NUTAN.K) COMBINATIONAL :-  1.MUX:- (one bit wide)  1a) 2:1 MUX and its Testbench   1b) 4:1 MUX using 2:1 and its testb...