module add2_5b (c1,s,a,b); input [4:0]a,b; output [4:0]s; output c1; fa ra1 (c0,s[0],a[0],b[0],1'b0); fa ra2 (c1,s[1],a[1],b[1],c0); fa ra3 (c2,s[2],a[2],b[2],c1); fa ra4 (c3,s[3],a[3],b[3],c2); fa ra5 (c1,s[4],a[4],b[4],c3); endmodule
TEST BENCH:-
module add2_5b_tb(); reg [4:0]a,b; wire [4:0]s; wire c; add2_5b dut (c,s,a,b); initial begin repeat(20) begin a=$random; b=$random; #1; $display({a}," ",{b},":",{c,s}); end end endmodule
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