MUX(2X1) ALL levels Verilog Code

2X1 MUX :-

STRUCTURAL LEVEL

//s-select line ; Y-output ;I0,I1 -input lines 

//1bit wide 2:1MUX (inputsI0,I1 &output Y, are of one bit only)

module mux2x1 (Y,s,I0,I1); 

input s,I1,I0;

output Y;

not n1 (a,s);

and a1 (x,a,I0);

and a2 (y,s,I1);

or  o1 (Y,x,y);

endmodule

DATA FLOW LEVEL

module mux2x1 (Y,s,I0,I1); 

input s,I1,I0;

output Y;

assign Y=((~s)&(I0))|((s)&(I1));

endmodule

BEHAVIOUR LEVEL

module mux2x1 (Y,s,I0,I1); 

input s,I1,I0;

output reg Y;

always@(s,I0,I1)

begin

case(s)

1'b0:Y=I0;

1'b1:Y=I1;

endcase

end

endmodule

2X1MUX_Testbench:-

module mux();

reg s,I1,I0;

wire Y;

mux2x1 dut (Y,s,I0,I1);

initial

 begin

   repeat (20)

    begin

     {s,I0,I1}=$random;

     #1;

     $display(s,":",I0,I1,":",Y);

    end

 end

endmodule