FULL ADDER:- 

module fa(cout,s,a,b,cin);
input a,b,cin;
output cout,s;
xor x1(s,a,b,cin);
and a1(c1,a,b);
and a2(c2,b,cin);
and a3(c3,cin,a);
or o1(cout,c1,c2,c3);
endmodule

TEST BENCH:- 

module adtb ();
reg a,b,cin;
wire cout,s;

fa dut (cout,s,a,b,cin);

integer j;
initial
begin
for (j=0;j<=7;j=j+1)
begin
{a,b,cin}= j;
#1;
$display(a,b,cin,":",cout,s);
end
end
endmodule