MUX4:1 using MUX2:1 (one bit wide) Structural level Verilog Code

 MUX 2:1:-

//s-select line ; Y-output ; I0,I1 -input lines

module mux2x1 (Y,s,I0,I1); 

//1bit wide 2:1MUX (inputsI0,I1 &output Y, are of one bit only)

input s,I1,I0;
output Y;

not n1 (a,s);
and a1 (x,a,I0);
and a2 (y,s,I1);
or  o1 (Y,x,y);

endmodule

 MUX 4:1:-

//s-select line ; Y-output ; I0,I1,I2,I3 -input lines

module mux4x1 (Y,s0,s1,I0,I1,I2,I3); //1bitwide_4:1MUX using 2:1MUX

input s0,s1,I1,I0,I2,I3;

output Y;

mux2x1 m1 (a,s0,I0,I1);

mux2x1 m2 (b,s0,I2,I3);

mux2x1 m3 (Y,s1,a,b);

endmodule

 MUX 4:1 Testbench:-

module mux();

reg s0,s1,I1,I0,I3,I2;
wire Y;

mux4x1 dut (Y,s0,s1,I0,I1,I2,I3);

initial

begin
   repeat (20)
   begin
    {s0,s1,I0,I1,I2,I3}=$random;
    #1;
    $display(s1,s0,":",I0,I1,I2,I3,":",Y);
   end

end
endmodule