11 i/p (1bit wide) ADDER:-

module add11 (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h,i,j,k);
input a,b,c,d,e,f,g,h,i,j,k;
output cout3,cout2,cout1,s;
add10 ad1 (c3,c2,c1,s1,a,b,c,d,e,f,g,h,i,j);
ha h1 (c4,s,s1,k);
ha h2 (c5,cout1,c4,c1);
ha h3 (c6,cout2,c5,c2);
ha h4 (c7,cout3,c6,c3);
endmodule

 TEST BENCH:-

module adtb ();
reg a,b,c,d,e,f,g,h,i,j,k;
wire cout3,cout2,cout1,s;
add11 dut (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h,i,j,k);
integer z;
initial
begin
for (z=0;z<=2047;z=z+1)
begin
{a,b,c,d,e,f,g,h,i,j,k}= z;
#1;
$display(a,b,c,d,e,f,g,h,i,j,k,":",cout3,cout2,cout1,s);
end
end
endmodule

 10 i/p (1bit wide) ADDER:-

module add10 (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h,i,j);
input a,b,c,d,e,f,g,h,i,j;
output cout3,cout2,cout1,s;
add9 ad1 (c3,c2,c1,s1,a,b,c,d,e,f,g,h,i);
ha h1 (c4,s,s1,j);
ha h2 (c5,cout1,c4,c1);
ha h3 (c6,cout2,c5,c2);
ha h4 (c7,cout3,c6,c3);
endmodule

 TEST BENCH:-

module adtb ();
reg a,b,c,d,e,f,g,h,i,j;
wire cout3,cout2,cout1,s;
add10 dut (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h,i,j);
integer z;
initial
begin
for (z=0;z<=1023;z=z+1)
begin
{a,b,c,d,e,f,g,h,i,j}= z;
#1;
$display(a,b,c,d,e,f,g,h,i,j,":",cout3,cout2,cout1,s);
end
end
endmodule

 9 i/p ADDER (1bit wide) :-

module add9 (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h,i);
input a,b,c,d,e,f,g,h,i;
output cout3,cout2,cout1,s;
add8 ad1 (c3,c2,c1,s1,a,b,c,d,e,f,g,h);
ha h1 (c4,s,s1,i);
ha h2 (c5,cout1,c4,c1);
ha h3 (c6,cout2,c5,c2);
ha h4 (c7,cout3,c6,c3);
endmodule

TEST BENCH :-

module adtb ();
reg a,b,c,d,e,f,g,h,i;
wire cout2,cout1,s;
add9 dut (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h,i);
integer z;
initial
begin
for (z=0;z<=511;z=z+1)
begin
{a,b,c,d,e,f,g,h,i}= z;
#1;
$display(a,b,c,d,e,f,g,h,i,":",cout3,cout2,cout1,s);
end
end
endmodule

  8 i/p (1bit wide) ADDER:-

module add8 (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h);
input a,b,c,d,e,f,g,h;
output cout3,cout2,cout1,s;
add7 ad1 (c2,c1,s1,a,b,c,d,e,f,g);
ha h1 (c3,s,s1,h);
ha h2 (c4,cout1,c3,c1);
ha h3 (cout3,cout2,c4,c2);
endmodule

Testbench :-

module adtb ();
reg a,b,c,d,e,f,g,h;
wire cout2,cout1,s;
add8 dut (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h);
integer j;
initial
begin
for (j=0;j<=255;j=j+1)
begin
{a,b,c,d,e,f,g,h}= j;
#1;
$display(a,b,c,d,e,f,g,h,":",cout3,cout2,cout1,s);
end
end
endmodule

 7 i/p (1bit wide) ADDER:-

module add7 (cout2,cout1,s,a,b,c,d,e,f,g);
input a,b,c,d,e,f,g;
output cout2,cout1,s;
add6 ad1 (c2,c1,s1,a,b,c,d,e,f);
ha h1 (c3,s,s1,g);
ha h2 (c4,cout1,c3,c1);
ha h3 (c5,cout2,c4,c2);
endmodule

 Testbench :-

module adtb ();

reg a,b,c,d,e,f,g;

wire cout2,cout1,s;

add7 dut (cout2,cout1,s,a,b,c,d,e,f,g);

integer j;

initial

begin

for (j=0;j<=127;j=j+1)

begin

{a,b,c,d,e,f,g}= j;

#1;

$display(a,b,c,d,e,f,g,":",cout2,cout1,s);

end

end

endmodule

 6 i/p - 1bit wide ADDER:-

module add6 (cout2,cout1,s,a,b,c,d,e,f);
input a,b,c,d,e,f;
output cout2,cout1,s;
xlfa xl1 (c2,c1,s1,a,b,c,d,e);
ha h1 (c3,s,s1,f);
ha h2 (c4,cout1,c3,c1);
ha h3 (c5,cout2,c4,c2);
endmodule

 Test Bench:-

module adtb ();
reg a,b,c,d,e,f;
wire cout2,cout1,s;
add6 dut (cout2,cout1,s,a,b,c,d,e,f);
integer j;
initial
begin
for (j=0;j<=63;j=j+1)
begin
{a,b,c,d,e,f}= j;
#1;
$display(a,b,c,d,e,f,":",cout2,cout1,s);
end
end
endmodule

 XL-FA :- (5i/p -1bitwide adder):-

module xlfa(cout2,cout1,s,a,b,c,d,e);
input a,b,c,d,e;
output cout2,cout1,s;
xfa xf1 (c2,c1,s1,a,b,c,d); 
ha h1 (c3,s,s1,e);
ha h2 (c4,cout1,c3,c1);
ha h3 (c5,cout2,c4,c2);
endmodule

Test bench:-

module adtb ();
reg a,b,c,d,e;
wire cout2,cout1,s;
xlfa dut (cout2,cout1,s,a,b,c,d,e);
integer j;
initial
begin
for (j=0;j<=31;j=j+1)
begin
{a,b,c,d,e}= j;
#1;
$display(a,b,c,d,e,":",cout2,cout1,s);
end
end
endmodule

 X-FULL ADDER:- (4i/p-1bitwide adder)

module xfa (cout2,cout1,s,a,b,c,d); 
input a,b,c,d;
output cout2,cout1,s;
wire c1,s1,c2;
fa f1 (c1,s1,a,b,c);
ha h1 (c2,s,s1,d);
ha h2 (cout2,cout1,c1,c2);
endmodule

 TEST BENCH:-

module adtb ();

reg a,b,c,d;
wire cout2,cout1,s;
xfa dut (cout2,cout1,s,a,b,c,d); 
integer j;
initial
begin
for (j=0;j<=15;j=j+1)
begin
{a,b,c,d}= j;
#1;
$display(a,b,c,d,":",cout2,cout1,s);
end
end
endmodule

FULL ADDER:- 

module fa(cout,s,a,b,cin);
input a,b,cin;
output cout,s;
xor x1(s,a,b,cin);
and a1(c1,a,b);
and a2(c2,b,cin);
and a3(c3,cin,a);
or o1(cout,c1,c2,c3);
endmodule

TEST BENCH:- 

module adtb ();
reg a,b,cin;
wire cout,s;

fa dut (cout,s,a,b,cin);

integer j;
initial
begin
for (j=0;j<=7;j=j+1)
begin
{a,b,cin}= j;
#1;
$display(a,b,cin,":",cout,s);
end
end
endmodule

 HALF ADDER:- 

module ha(c,s,a,b);
input a,b;
output s,c;
xor x1(s,a,b);
and a1 (c,a,b);
endmodule

Testbench:- 

module hatb ();
reg a,b;
wire c,s;
ha dut (c,s,a,b);
integer i;
initial
begin
for (i=0;i<=3;i=i+1)
begin
{a,b}= i;
#1;
$display(a,b,":",c,s);
end
end
endmodule

VERILOG CODES :-

 VERILOG CODES :- (by NUTAN.K)

COMBINATIONAL :- 

1.MUX:- (one bit wide)

 1a) 2:1 MUX and its Testbench 

 1b) 4:1 MUX using 2:1 and its testbench

2.MUX:- (input bit wide)

 2a) 2:1 MUX (3bit wide) and its Testbench 

3.ADDERS :-

3a) Half adder and its testbench

3b) Full adder and its testbench

3c)  X-Full adder and its test bench

3d) XL-Full adder and its test bench

3e) 6i/p adder (1bit wide) and its testbench

3f) 7i/p adder (1bit wide) and its testbench

3g) 8i/p adder (1bit wide) and its testbench

3h) 9i/p adder (1bit wide) and its testbench

3i) 10i/p adder (1 bit wide) and its testbench

3j) 11 i/p adder (1bit wide) and its testbench

3k) 2 i/p adder (5bit wide) and its testbench

3l) 2 i/p adder (1bit,5bit wide) and its testbench

4.SUBTRACTORS :-

4a) 2 i/p subtractor (5bitwide) and its testbench

5.COMPARATORS :-

5a) Two i/p comparator (one bit wide)

5b) Two i/p comparator (two bit wide)

5c) Two i/p comparator (four bit wide)

MUX4:1 using MUX2:1 (one bit wide) Structural level Verilog Code

 MUX 2:1:-

//s-select line ; Y-output ; I0,I1 -input lines

module mux2x1 (Y,s,I0,I1); 

//1bit wide 2:1MUX (inputsI0,I1 &output Y, are of one bit only)

input s,I1,I0;
output Y;

not n1 (a,s);
and a1 (x,a,I0);
and a2 (y,s,I1);
or  o1 (Y,x,y);

endmodule

 MUX 4:1:-

//s-select line ; Y-output ; I0,I1,I2,I3 -input lines

module mux4x1 (Y,s0,s1,I0,I1,I2,I3); //1bitwide_4:1MUX using 2:1MUX

input s0,s1,I1,I0,I2,I3;

output Y;

mux2x1 m1 (a,s0,I0,I1);

mux2x1 m2 (b,s0,I2,I3);

mux2x1 m3 (Y,s1,a,b);

endmodule

 MUX 4:1 Testbench:-

module mux();

reg s0,s1,I1,I0,I3,I2;
wire Y;

mux4x1 dut (Y,s0,s1,I0,I1,I2,I3);

initial

begin
   repeat (20)
   begin
    {s0,s1,I0,I1,I2,I3}=$random;
    #1;
    $display(s1,s0,":",I0,I1,I2,I3,":",Y);
   end

end
endmodule

MUX(2X1) ALL levels Verilog Code

2X1 MUX :-

STRUCTURAL LEVEL

//s-select line ; Y-output ;I0,I1 -input lines 

//1bit wide 2:1MUX (inputsI0,I1 &output Y, are of one bit only)

module mux2x1 (Y,s,I0,I1); 

input s,I1,I0;

output Y;

not n1 (a,s);

and a1 (x,a,I0);

and a2 (y,s,I1);

or  o1 (Y,x,y);

endmodule

DATA FLOW LEVEL

module mux2x1 (Y,s,I0,I1); 

input s,I1,I0;

output Y;

assign Y=((~s)&(I0))|((s)&(I1));

endmodule

BEHAVIOUR LEVEL

module mux2x1 (Y,s,I0,I1); 

input s,I1,I0;

output reg Y;

always@(s,I0,I1)

begin

case(s)

1'b0:Y=I0;

1'b1:Y=I1;

endcase

end

endmodule

2X1MUX_Testbench:-

module mux();

reg s,I1,I0;

wire Y;

mux2x1 dut (Y,s,I0,I1);

initial

 begin

   repeat (20)

    begin

     {s,I0,I1}=$random;

     #1;

     $display(s,":",I0,I1,":",Y);

    end

 end

endmodule