TWO i/p (8bitwide) COMPARATOR:- 

module comp8 (gt8,eq8,lt8,A8,B8);
input[7:0]A8,B8;
output gt8,eq8,lt8;
wire [2:0]Y22;
wire a8,b8,c8,d8,e8,f8;
comp4 co11 (a8,b8,c8,{A8[7],A8[6],A8[5],A8[4]},{B8[7],B8[6],B8[5],B8[4]});
comp4 co22 (d8,e8,f8,{A8[3],A8[2],A8[1],A8[0]},{B8[3],B8[2],B8[1],B8[0]});
mux2x1_3b mm1 ({gt8,eq8,lt8},a8,Y22,3'b100);
mux2x1_3b mm2 (Y22,c8,{d8,e8,f8},3'b001);
endmodule

TEST BENCH:- 

module comp8_tb();
reg [7:0]A8,B8;
wire gt8,eq8,lt8;
comp8 dut (gt8,eq8,lt8,A8,B8);
initial
begin
repeat(20)
begin
{A8,B8}=$random;
#2
$display("A=",{A8}," B=",{B8},":"," greater:",gt8," equal:",eq8," lesser:",lt8);
end
end
endmodule

 

2I/P- 5BIT WIDE SUBTRACTOR 

module sub_5b (bor,diff,A,B);
input [4:0] A,B;
output [4:0]diff;
output bor;
wire[4:0]b1,b2;

not n1 (b1[0],B[0]);//(1scomp)
not n2 (b1[1],B[1]);//(1scomp)
not n3 (b1[2],B[2]);//(1scomp)
not n4 (b1[3],B[3]);//(1scomp)
not n5 (b1[4],B[4]);//(1scomp)

add2_5b ad1 (unused,b2,5'b00001,b1);  //(1scomp+1)

add2_5b ad2 (bor,diff,A,b2); //((2scomp of B) + A)
endmodule 

logic:- 1st do 1s comp and perform 2s comp for B and add with A. 

sub modules :- 5 i/p adder module

TEST BENCH:-

module sub2_5b_tb();
reg [4:0]A,B;
wire [4:0]diff;
wire bor;
sub_5b dut (bor,diff,A,B);
initial
begin
repeat(20)
begin
A=$random;
B=$urandom_range(A,0);
#1;
$display({A}," ",{B},":",{diff});
end
end
endmodule

  

 

TWO i/p (4bitwide) COMPARATOR:- 

module comp4 (gt4,eq4,lt4,A4,B4);
input[3:0]A4,B4;
output gt4,eq4,lt4;
wire [2:0]Y1;
wire a4,b4,c4,d4,e4,f4;
comp2 co1 (a4,b4,c4,{A4[3],A4[2]},{B4[3],B4[2]});
comp2 co2 (d4,e4,f4,{A4[1],A4[0]},{B4[1],B4[0]});
mux2x1_3b m1 ({gt4,eq4,lt4},a4,Y1,3'b100);
mux2x1_3b m2 (Y1,c4,{d4,e4,f4},3'b001);
endmodule

TEST BENCH:- 

module comp4_tb();
reg [3:0]A4,B4;
wire gt4,eq4,lt4;
comp4 dut (gt4,eq4,lt4,A4,B4);
initial
begin
repeat(20)
begin
{A4,B4}=$random;
#2
$display("A=",{A4}," B=",{B4},":"," greater:",gt4," equal:",eq4," lesser:",lt4);
end
end
endmodule

 

 

TWO i/p (2bitwide) COMPARATOR:- 

module comp2(gt2,eq2,lt2,A2,B2);
input[1:0]A2,B2;
output gt2,eq2,lt2;
wire [2:0]Y1;
wire a,b,c,d,e,f;
comp1  c1 (a,b,c,A2[1],B2[1]);
comp1  c2  (d,e,f,A2[0],B2[0]);
mux2x1_3b m1 ({gt2,eq2,lt2},a,Y1,3'b100);
mux2x1_3b m2 (Y1,c,{d,e,f},3'b001);
endmodule

TEST BENCH:- 

module comp2_tb();
reg [1:0]A2,B2;
wire gt2,eq2,lt2;
comp2 dut (gt2,eq2,lt2,A2,B2);
initial
begin
repeat(20)
begin
{A2,B2}=$random;
#2
$display("A=",{A2}," B=",{B2},":","greater:",gt2,"equal:",eq2,"lesser:",lt2);
end
end
endmodule

MUX2x1(3bit wide):-

  MUX 2:1 :-

//s-select line ; Y-output ; I0,I1 -input lines

module mux2x1 (y,s,i0,i1); 
input s,i1,i0;
output y;
assign y=((~s)&(i0))+((s)&(i1));
endmodule

 MUX2x1(3bit wide):-

module mux2x1_3b(Y,s,I0,I1);
input[2:0]I0,I1;
input s;
output [2:0]Y;
mux2x1 m1 (Y[0],s,I0[0],I1[0]); 
mux2x1 m2 (Y[1],s,I0[1],I1[1]); 
mux2x1 m3 (Y[2],s,I0[2],I1[2]);
endmodule 

 MUX 4:1 Testbench:-

module mux2x1_3b_tb();
reg s;
reg [2:0] I1,I0;
wire [2:0] Y;
mux2x1_3b dut (Y,s,I0,I1);
initial
begin
repeat(20)
begin
{s,I0,I1}=$random;
#2
$display(s,I0,I1,":",Y);
end
end
endmodule

 

2I/P- A-1bit; B-5BIT WIDE ADDER 

module add2_5b (co1,s,a,b);
input [4:0]b;
input a;
output [4:0]s;
output co1;
fa ra1 (c0,s[0],a,b[0],1'b0);
fa ra2 (c1,s[1],1'b0,b[1],c0);
fa ra3 (c2,s[2],1'b0,b[2],c1);
fa ra4 (c3,s[3],1'b0,b[3],c2);
fa ra5 (co1,s[4],1'b0,b[4],c3);
endmodule

TEST BENCH:-

module add2_5b_tb();
reg [4:0]a,b;
wire [4:0]s;
wire c;
add2_5b dut (c,s,a,b);
initial
begin
repeat(20)
begin
a=$random;
b=$random;
#1;
$display({a}," ",{b},":",{c,s});
end
end
endmodule

2I/P- 5BIT WIDE ADDER 

module add2_5b (c1,s,a,b);
input [4:0]a,b;
output [4:0]s;
output c1;
fa ra1 (c0,s[0],a[0],b[0],1'b0);
fa ra2 (c1,s[1],a[1],b[1],c0);
fa ra3 (c2,s[2],a[2],b[2],c1);
fa ra4 (c3,s[3],a[3],b[3],c2);
fa ra5 (c1,s[4],a[4],b[4],c3);
endmodule

TEST BENCH:-

module add2_5b_tb();
reg [4:0]a,b;
wire [4:0]s;
wire c;
add2_5b dut (c,s,a,b);
initial
begin
repeat(20)
begin
a=$random;
b=$random;
#1;
$display({a}," ",{b},":",{c,s});
end
end
endmodule

 

TWO BIT COMPARATOR:- 

(one bit wide)

module comp1 (gt,eq,lt,a,b);
input a,b;
output gt,eq,lt;
not G1(abar,a);
not G2(bbar,b);
and G3(gt,a,bbar);
and G4(lt,abar,b);
xnor G5(eq,a,b);
endmodule

TEST BENCH:- 

module comp1_tb();

reg a,b;
wire gt,eq,lt;
comp1 dut (gt,eq,lt,a,b);
initial
begin
repeat(20)
begin
a=$random;
b=$random;
#1;
$display(a,b,":",gt,eq,lt);
end
end
endmodule

 8X8 MULTIPLIER:-

module mul8(Y,a,b);
input [7:0]a,b;
output [16:0]Y;

and g00 (Y[0],a[0],b[0]);
and g01 (p01 ,a[1],b[0]);
and g02 (p02 ,a[2],b[0]);
and g03 (p03 ,a[3],b[0]);
and g04 (p04 ,a[4],b[0]);
and g05 (p05 ,a[5],b[0]);
and g06 (p06 ,a[6],b[0]);
and g07 (p07 ,a[7],b[0]);

and g10 (p10,a[0],b[1]);
and g11 (p11 ,a[1],b[1]);
and g12 (p12 ,a[2],b[1]);
and g13 (p13 ,a[3],b[1]);
and g14 (p14 ,a[4],b[1]);
and g15 (p15 ,a[5],b[1]);
and g16 (p16 ,a[6],b[1]);
and g17 (p17 ,a[7],b[1]);

and g20 (p20,a[0],b[2]);
and g21 (p21 ,a[1],b[2]);
and g22 (p22 ,a[2],b[2]);
and g23 (p23 ,a[3],b[2]);
and g24 (p24 ,a[4],b[2]);
and g25 (p25 ,a[5],b[2]);
and g26 (p26 ,a[6],b[2]);
and g27 (p27 ,a[7],b[2]);

and g30 (p30,a[0],b[3]);
and g31 (p31 ,a[1],b[3]);
and g32 (p32 ,a[2],b[3]);
and g33 (p33 ,a[3],b[3]);
and g34 (p34 ,a[4],b[3]);
and g35 (p35 ,a[5],b[3]);
and g36 (p36 ,a[6],b[3]);
and g37 (p37 ,a[7],b[3]);
and g40 (p40,a[0],b[4]);
and g41 (p41 ,a[1],b[4]);
and g42 (p42 ,a[2],b[4]);
and g43 (p43 ,a[3],b[4]);
and g44 (p44 ,a[4],b[4]);
and g45 (p45 ,a[5],b[4]);
and g46 (p46 ,a[6],b[4]);
and g47 (p47 ,a[7],b[4]);
and g50 (p50,a[0],b[5]);
and g51 (p51 ,a[1],b[5]);
and g52 (p52 ,a[2],b[5]);
and g53 (p53 ,a[3],b[5]);
and g54 (p54 ,a[4],b[5]);
and g55 (p55 ,a[5],b[5]);
and g56 (p56 ,a[6],b[5]);
and g57 (p57 ,a[7],b[5]);
and g60 (p60,a[0],b[6]);
and g61 (p61 ,a[1],b[6]);
and g62 (p62 ,a[2],b[6]);
and g63 (p63 ,a[3],b[6]);
and g64 (p64 ,a[4],b[6]);
and g65 (p65 ,a[5],b[6]);
and g66 (p66 ,a[6],b[6]);
and g67 (p67 ,a[7],b[6]);
and g70 (p70,a[0],b[7]);
and g71 (p71 ,a[1],b[7]);
and g72 (p72 ,a[2],b[7]);
and g73 (p73 ,a[3],b[7]);
and g74 (p74 ,a[4],b[7]);
and g75 (p75 ,a[5],b[7]);
and g76 (p76 ,a[6],b[7]);
and g77 (p77 ,a[7],b[7]);
ha a1 (c1,Y[1],p10,p01);
xfa a2 (c21,c20,Y[2],p20,c1,p11,p02); 
xlfa a3 (c31,c30,Y[3],c20,p30,p21,p12,p03);
add7  a4 (c41,c40,Y[4],c21,c30,p40,p31,p22,p13,p04);
add8 a5 (c52,c51,c50,Y[5],c31,c40,p50,p41,p32,p23,p14,p05);
add9 a6 (c62,c61,c60,Y[6],c41,c50,p60,p51,p42,p33,p24,p15,p06);
add10 a7 (c72,c71,c70,Y[7],c51,c60,p70,p61,p52,p43,p34,p25,p16,p07);
add10 a8 (c82,c81,c80,Y[8],c52,c61,c70,p71,p62,p53,p44,p35,p26,p17);
add9 a9 (c92,c91,c90,Y[9],c71,c62,c80,p72,p63,p54,p45,p36,p27);
add8 a10 (c102,c101,c100,Y[10],c90,c81,c72,p73,p64,p55,p46,p37);
add7 a11 (c111,c110,Y[11],c100,c91,c82,p74,p65,p56,p47);
add6 a12 (c121,c120,Y[12],c110,c101,c92,p75,p66,p57);
xlfa a13 (c131,c130,Y[13],c120,c111,c102,p76,p66);
fa   a14 (c140,Y[14],c130,c121,p77);
ha   a15 (c150,Y[15],c140,c131); 
ha   a16  (c160,Y[16],c150,1'b0);
endmodule

TEST BENCH:-

module adtb ();
reg [7:0]a,b;
wire [16:0]Y;
mul8 dut (Y,a,b);
initial
repeat(20)
begin
a=$random;
b=$random;
#1;
//$display("%b %b %b ", a,b,Y);
#1;
$display(a, " x " ," ", b ," : ", Y);
end
endmodule

 11 i/p (1bit wide) ADDER:-

module add11 (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h,i,j,k);
input a,b,c,d,e,f,g,h,i,j,k;
output cout3,cout2,cout1,s;
add10 ad1 (c3,c2,c1,s1,a,b,c,d,e,f,g,h,i,j);
ha h1 (c4,s,s1,k);
ha h2 (c5,cout1,c4,c1);
ha h3 (c6,cout2,c5,c2);
ha h4 (c7,cout3,c6,c3);
endmodule

 TEST BENCH:-

module adtb ();
reg a,b,c,d,e,f,g,h,i,j,k;
wire cout3,cout2,cout1,s;
add11 dut (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h,i,j,k);
integer z;
initial
begin
for (z=0;z<=2047;z=z+1)
begin
{a,b,c,d,e,f,g,h,i,j,k}= z;
#1;
$display(a,b,c,d,e,f,g,h,i,j,k,":",cout3,cout2,cout1,s);
end
end
endmodule

 10 i/p (1bit wide) ADDER:-

module add10 (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h,i,j);
input a,b,c,d,e,f,g,h,i,j;
output cout3,cout2,cout1,s;
add9 ad1 (c3,c2,c1,s1,a,b,c,d,e,f,g,h,i);
ha h1 (c4,s,s1,j);
ha h2 (c5,cout1,c4,c1);
ha h3 (c6,cout2,c5,c2);
ha h4 (c7,cout3,c6,c3);
endmodule

 TEST BENCH:-

module adtb ();
reg a,b,c,d,e,f,g,h,i,j;
wire cout3,cout2,cout1,s;
add10 dut (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h,i,j);
integer z;
initial
begin
for (z=0;z<=1023;z=z+1)
begin
{a,b,c,d,e,f,g,h,i,j}= z;
#1;
$display(a,b,c,d,e,f,g,h,i,j,":",cout3,cout2,cout1,s);
end
end
endmodule

 9 i/p ADDER (1bit wide) :-

module add9 (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h,i);
input a,b,c,d,e,f,g,h,i;
output cout3,cout2,cout1,s;
add8 ad1 (c3,c2,c1,s1,a,b,c,d,e,f,g,h);
ha h1 (c4,s,s1,i);
ha h2 (c5,cout1,c4,c1);
ha h3 (c6,cout2,c5,c2);
ha h4 (c7,cout3,c6,c3);
endmodule

TEST BENCH :-

module adtb ();
reg a,b,c,d,e,f,g,h,i;
wire cout2,cout1,s;
add9 dut (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h,i);
integer z;
initial
begin
for (z=0;z<=511;z=z+1)
begin
{a,b,c,d,e,f,g,h,i}= z;
#1;
$display(a,b,c,d,e,f,g,h,i,":",cout3,cout2,cout1,s);
end
end
endmodule

  8 i/p (1bit wide) ADDER:-

module add8 (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h);
input a,b,c,d,e,f,g,h;
output cout3,cout2,cout1,s;
add7 ad1 (c2,c1,s1,a,b,c,d,e,f,g);
ha h1 (c3,s,s1,h);
ha h2 (c4,cout1,c3,c1);
ha h3 (cout3,cout2,c4,c2);
endmodule

Testbench :-

module adtb ();
reg a,b,c,d,e,f,g,h;
wire cout2,cout1,s;
add8 dut (cout3,cout2,cout1,s,a,b,c,d,e,f,g,h);
integer j;
initial
begin
for (j=0;j<=255;j=j+1)
begin
{a,b,c,d,e,f,g,h}= j;
#1;
$display(a,b,c,d,e,f,g,h,":",cout3,cout2,cout1,s);
end
end
endmodule

 7 i/p (1bit wide) ADDER:-

module add7 (cout2,cout1,s,a,b,c,d,e,f,g);
input a,b,c,d,e,f,g;
output cout2,cout1,s;
add6 ad1 (c2,c1,s1,a,b,c,d,e,f);
ha h1 (c3,s,s1,g);
ha h2 (c4,cout1,c3,c1);
ha h3 (c5,cout2,c4,c2);
endmodule

 Testbench :-

module adtb ();

reg a,b,c,d,e,f,g;

wire cout2,cout1,s;

add7 dut (cout2,cout1,s,a,b,c,d,e,f,g);

integer j;

initial

begin

for (j=0;j<=127;j=j+1)

begin

{a,b,c,d,e,f,g}= j;

#1;

$display(a,b,c,d,e,f,g,":",cout2,cout1,s);

end

end

endmodule

 6 i/p - 1bit wide ADDER:-

module add6 (cout2,cout1,s,a,b,c,d,e,f);
input a,b,c,d,e,f;
output cout2,cout1,s;
xlfa xl1 (c2,c1,s1,a,b,c,d,e);
ha h1 (c3,s,s1,f);
ha h2 (c4,cout1,c3,c1);
ha h3 (c5,cout2,c4,c2);
endmodule

 Test Bench:-

module adtb ();
reg a,b,c,d,e,f;
wire cout2,cout1,s;
add6 dut (cout2,cout1,s,a,b,c,d,e,f);
integer j;
initial
begin
for (j=0;j<=63;j=j+1)
begin
{a,b,c,d,e,f}= j;
#1;
$display(a,b,c,d,e,f,":",cout2,cout1,s);
end
end
endmodule

 XL-FA :- (5i/p -1bitwide adder):-

module xlfa(cout2,cout1,s,a,b,c,d,e);
input a,b,c,d,e;
output cout2,cout1,s;
xfa xf1 (c2,c1,s1,a,b,c,d); 
ha h1 (c3,s,s1,e);
ha h2 (c4,cout1,c3,c1);
ha h3 (c5,cout2,c4,c2);
endmodule

Test bench:-

module adtb ();
reg a,b,c,d,e;
wire cout2,cout1,s;
xlfa dut (cout2,cout1,s,a,b,c,d,e);
integer j;
initial
begin
for (j=0;j<=31;j=j+1)
begin
{a,b,c,d,e}= j;
#1;
$display(a,b,c,d,e,":",cout2,cout1,s);
end
end
endmodule

 X-FULL ADDER:- (4i/p-1bitwide adder)

module xfa (cout2,cout1,s,a,b,c,d); 
input a,b,c,d;
output cout2,cout1,s;
wire c1,s1,c2;
fa f1 (c1,s1,a,b,c);
ha h1 (c2,s,s1,d);
ha h2 (cout2,cout1,c1,c2);
endmodule

 TEST BENCH:-

module adtb ();

reg a,b,c,d;
wire cout2,cout1,s;
xfa dut (cout2,cout1,s,a,b,c,d); 
integer j;
initial
begin
for (j=0;j<=15;j=j+1)
begin
{a,b,c,d}= j;
#1;
$display(a,b,c,d,":",cout2,cout1,s);
end
end
endmodule

FULL ADDER:- 

module fa(cout,s,a,b,cin);
input a,b,cin;
output cout,s;
xor x1(s,a,b,cin);
and a1(c1,a,b);
and a2(c2,b,cin);
and a3(c3,cin,a);
or o1(cout,c1,c2,c3);
endmodule

TEST BENCH:- 

module adtb ();
reg a,b,cin;
wire cout,s;

fa dut (cout,s,a,b,cin);

integer j;
initial
begin
for (j=0;j<=7;j=j+1)
begin
{a,b,cin}= j;
#1;
$display(a,b,cin,":",cout,s);
end
end
endmodule

 HALF ADDER:- 

module ha(c,s,a,b);
input a,b;
output s,c;
xor x1(s,a,b);
and a1 (c,a,b);
endmodule

Testbench:- 

module hatb ();
reg a,b;
wire c,s;
ha dut (c,s,a,b);
integer i;
initial
begin
for (i=0;i<=3;i=i+1)
begin
{a,b}= i;
#1;
$display(a,b,":",c,s);
end
end
endmodule

VERILOG CODES :-

 VERILOG CODES :- (by NUTAN.K)

COMBINATIONAL :- 

1.MUX:- (one bit wide)

 1a) 2:1 MUX and its Testbench 

 1b) 4:1 MUX using 2:1 and its testbench

2.MUX:- (input bit wide)

 2a) 2:1 MUX (3bit wide) and its Testbench 

3.ADDERS :-

3a) Half adder and its testbench

3b) Full adder and its testbench

3c)  X-Full adder and its test bench

3d) XL-Full adder and its test bench

3e) 6i/p adder (1bit wide) and its testbench

3f) 7i/p adder (1bit wide) and its testbench

3g) 8i/p adder (1bit wide) and its testbench

3h) 9i/p adder (1bit wide) and its testbench

3i) 10i/p adder (1 bit wide) and its testbench

3j) 11 i/p adder (1bit wide) and its testbench

3k) 2 i/p adder (5bit wide) and its testbench

3l) 2 i/p adder (1bit,5bit wide) and its testbench

4.SUBTRACTORS :-

4a) 2 i/p subtractor (5bitwide) and its testbench

5.COMPARATORS :-

5a) Two i/p comparator (one bit wide)

5b) Two i/p comparator (two bit wide)

5c) Two i/p comparator (four bit wide)

MUX4:1 using MUX2:1 (one bit wide) Structural level Verilog Code

 MUX 2:1:-

//s-select line ; Y-output ; I0,I1 -input lines

module mux2x1 (Y,s,I0,I1); 

//1bit wide 2:1MUX (inputsI0,I1 &output Y, are of one bit only)

input s,I1,I0;
output Y;

not n1 (a,s);
and a1 (x,a,I0);
and a2 (y,s,I1);
or  o1 (Y,x,y);

endmodule

 MUX 4:1:-

//s-select line ; Y-output ; I0,I1,I2,I3 -input lines

module mux4x1 (Y,s0,s1,I0,I1,I2,I3); //1bitwide_4:1MUX using 2:1MUX

input s0,s1,I1,I0,I2,I3;

output Y;

mux2x1 m1 (a,s0,I0,I1);

mux2x1 m2 (b,s0,I2,I3);

mux2x1 m3 (Y,s1,a,b);

endmodule

 MUX 4:1 Testbench:-

module mux();

reg s0,s1,I1,I0,I3,I2;
wire Y;

mux4x1 dut (Y,s0,s1,I0,I1,I2,I3);

initial

begin
   repeat (20)
   begin
    {s0,s1,I0,I1,I2,I3}=$random;
    #1;
    $display(s1,s0,":",I0,I1,I2,I3,":",Y);
   end

end
endmodule

MUX(2X1) ALL levels Verilog Code

2X1 MUX :-

STRUCTURAL LEVEL

//s-select line ; Y-output ;I0,I1 -input lines 

//1bit wide 2:1MUX (inputsI0,I1 &output Y, are of one bit only)

module mux2x1 (Y,s,I0,I1); 

input s,I1,I0;

output Y;

not n1 (a,s);

and a1 (x,a,I0);

and a2 (y,s,I1);

or  o1 (Y,x,y);

endmodule

DATA FLOW LEVEL

module mux2x1 (Y,s,I0,I1); 

input s,I1,I0;

output Y;

assign Y=((~s)&(I0))|((s)&(I1));

endmodule

BEHAVIOUR LEVEL

module mux2x1 (Y,s,I0,I1); 

input s,I1,I0;

output reg Y;

always@(s,I0,I1)

begin

case(s)

1'b0:Y=I0;

1'b1:Y=I1;

endcase

end

endmodule

2X1MUX_Testbench:-

module mux();

reg s,I1,I0;

wire Y;

mux2x1 dut (Y,s,I0,I1);

initial

 begin

   repeat (20)

    begin

     {s,I0,I1}=$random;

     #1;

     $display(s,":",I0,I1,":",Y);

    end

 end

endmodule

(please comment your answer)

 Is DIODE current is Drift or Diffusion ?.......

WHY A STEP-UP TRANSFORMER CANT BE USED AS AN AMPLIFIER?

As you can see in the above figure, for a step-up transformer the amplitude of the output waveform is greater than the input waveform (due to more number of turns on the secondary side of the transformer)

But in the case of the amplifier,

the output voltage the amplifier is also greater than the input voltage.

so there is generally a confusion among most of us that both perform the same operation but in reality its not same operation.

Many of us think that since it is not easy to construct an amplifier.

In the transformer ratio formula, there is an inverse relationship between the current and voltage.

A step-up transformer (Ns>Np) increases the voltage in the secondary coil, at the same time the current in the secondary coil of the transformer gets decreased. (that can be seen by the transformer formula given above)

POWER aT PRIMARY COIL = POWER at SECONDARY COIL 

INPUT POWER =OUTPUT POWER  

(for a Transformer)

But in the case of the Amplifier, there is 

amplification in both the voltage and current

so the 

OUTPUT POWER > INPUT POWER

 so the real amplification is taking place  here

AUTOMATIC STREET LIGHTS:-

In our daily life we see glowing of street lights even though there is sufficient light outside.There is a lot of wastage of energy occurring due to this.

Thus to avoid this energy wastage ,the circuit shown below can reduce this and save lot of energy in this circuit we use the light sensor names LDR (LIGHT DEPENDANT RESISTANCE) as shown below to detect the presence of light .

now first we learn about,

How an LDR (Light Dependent Resistor) Works ?

An LDR is a component whose value of resistance ,changes with the light intensity that falls upon it. This allows them to be used in light sensing circuits.

A typical LDR looks like as shown below,

The symbol for LDR looks like as shown in the below picture

when there is abundance of light there is a low resistance in the the LDR because all the electrons gain energy from incident light (photons)go to conduction band and participate in the conduction,

but in the absence of light there is no sufficient energy for the electrons to go to the conduction band so there is no available free electrons for conduction,so it acts as high resistance .The curve showing the variation of resistance in shown in the figure  below  

CIRCUIT DIAGRAM

FOR USING LDR IN AUTOMATIC STREET LIGHT SYSTEM

In the above circuit we use the help of transistor, the LDR is connected between the Base and emitter,consider the case when there is light .

since there is light there is low resistance of LDR so there is less voltage drop across LDR.This voltage drop across LDR is equal to voltage across "Vbe",this "Vbe" cannot drive the transistor into ON condition.So there wont be any collector current,So LED  dosen't glow.

While in another case , when there is no light the LDR  becomes very high resistive and there will be a high voltage drop across the LDR, this implies high drop across the  "Vbe".So the transistor turns ON and there will be collector current by which "LED GLOWS"

This  is how we made use of light sensor and transistor for our convenience.

In practical application the street light can be used in the place of LED

Other Applications of LDRs:-

Camera shutter control

LDRs can be used to control the shutter speed on a camera. The LDR would be used to measure the light intensity which then adjusts the camera shutter speed to the appropriate level.

why AC(alternating current) cant be stored ,like DC in batteries ?

The AC(alternating current) is the current or voltage whose magnitude (generally 230V in India and 100V in US) varies with time with some frequency (generally 50Hzs in India and 60Hzs in US) , but in the case of DC the magnitude of the is constant with time (like a step function).so DC has no frequency. 

       
                          

                                       DC-Voltage

we can see from the above pictures that the AC varies with time but DC is constant, moreover the DC voltage has a average value, but the average value of the AC voltage is zero for full cycle.The capacitor can store only DC voltage because average value is equal to the dc voltage,but in the case of the AC voltage,we  cant store because it average value is equal to zero.

      Here we are considering the case of capacitor only because all the practical batteries are nothing but capacitors which can with stand based on their voltage ranges. 

# So for this reason we are interested in storing in DC voltages only

THE STORY BEHIND 15TH SEPTEMBER

THE STORY BEHIND 15TH SEPTEMBER

 ---NUTAN SATYA SAI RAJ .K   
  Every story has a hero.The hero of our story is Sir Mokshagundam Visveswaraya!!!                                                         

                                                 

        Sir Mokshagundam Visvesvaraya is an Eminent Civil Engineer and Excellent Statesman. He is the oldest surviving icon from 20th Century. He was born in a poor brahmin family in Muddenahalli in 1860.He was an engineer with a flair for bold and creative ideas. His studies and research concentrated mainly on flow of water and building dams. He has the credit of inventing ‘Automatic Flood Gates System’ and ‘Block Irrigation System’ which are still considered to be marvels in engineering and they were considered as best design in Asia in 1903.

          Once Mokshagundam Visvesvaraya, as Chief Engineer for Karnataka state visited beautiful Sivasamudra Waterfalls, located in Karnataka over the bank of river Kaveri. After watching them, he made a comment immediately, "What a huge waste of Energy?”. Every one present over there was shocked by the statement. In a flash, he got an idea to build a Hydro-electricity Project over there. His eyes didn't see the beauty of the water falls but only saw the loss of Energy. Hence, we can understand the dedication levels of an ideal engineer present in him!

           

           He also holds the credit of planning the ghat-road from Tirupati to Tirumala. The greatest thing about that is, there was no single rock fall and accidents occurred till today on that road. But surprisingly, some rock fall and accidents occurred on the other road which was constructed by new generation engineers. Visveswaraya sir planned the road in such a way that he observed each and every corner of the mountain for few months and designed efficiently with utmost care. Thus we can see a high level quality engineer present in him!

Have you ever heard about floods in Hyderabad?  Surely the answer is NO. It is all because our greatest engineer Visveswaraya Sir. In 1908 there were severe floods to Musi river in Hyderabad. Almost 50,500 people died and many became homeless. Then he developed flood protection system by designing and constructing the dam and drainage systems in Hyderabad. With his engineering skills, he turned Hyderabad to flood-free city. He also saved the Visakhapatnam port from sea erosion. The part of the port which was constructed by him was very less affected even from the recent Hudhud cyclone. This shows his expertise!

He built Krishna Raja Sagar Dam which is the largest Dam in Asia at the time of its construction. It is considered as one of the greatest achievements. At the age of 90, Visveswaraya sir constructed a bridge over river Ganga in Bihar. Thus we can understand level of interest present in him. He said that “Engineer is a person who creates things which are not created by God”. These are a few of his great works done by him. He is an engineer with a great passion! "Work is Worship" is the motto of Sir Visveswaraya!

The Indian government considering his greatness honoured him with Bharat Ratna in the year 1955 and didn't find an engineer like him and therefore celebrates his birthday 15th September as National Engineers Day every year. There are 1.3 billion Indians, 1.5 million are engineers. And yet, most of us are unaware of the only day dedicated to this pioneering community of our country. This article focuses a great Indian engineer Sir Mokshagundam Visveswaraya. It is the minimum responsibility of every engineer to know about the greatness of him and adopt the qualities of him.I consider my standards are not sufficient to describe the greatness of Visveswaraya Sir, but I am still fortunate in trying my level best in writing this article and I wish a very Happy Engineer’s Day in advance to all our budding and expert innovators reforming our Nation.

" Remember your work may be only to sweep railway crossing but it is your duty to keep it so clean that no other crossing in the world is as clean as yours."   --- Sir Mokshadundam Visveswaraya.

                             A video on visveswaraya sir in social media                                                                 

Learn AURDINO:-

Here is the book for Beginning AURDINO.

Enjoy learning!!!!

click_here to download the book.

TEXT BOOKS FOR ECE

BEST TEXTBOOKS FOR   ECE:-

All the standard textbooks are given subject wise below. The best books preferred for each subject are given, students can see and download the book based on their understanding.

click on the respective subject name to see and download textbooks.

1.ELECTRONIC DEVICES AND CIRCUITS

2.NETWORK ANALYSIS

3.DIGITAL ELECTRONICS

4.SIGNALS AND SYSTEMS

5.ANALOG ELECTRONICS

6.CONTROL SYSTEMS

7.LICA

8.MICROPROCESSORS

9.VERILOG HDL

10.ANALOG AND DIGITAL COMMUNICATIONS

11.ANTENNA THEORY AND DESIGN

12. ELECTROMAGNETICS

13.C-LANGUAGE

14.JAVA

15.QUANTUM MECHANICS

16.VLSI

17. QUANTITATIVE APTITUDE